View NCP1282_707353.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

NCP1282 High Performance Active Clamp/Reset PWM Controller Featuring 500 V Startup
The NCP1282 is a voltage mode controller designed for ac-dc or dc-dc converters requiring high-efficiency and low parts count. This controller incorporates two in phase outputs with an overlap delay to prevent simultaneous conduction and facilitates soft switching. The main output is designed for driving a forward converter primary MOSFET. The secondary output is designed for driving an active clamp circuit MOSFET, a synchronous rectifier on the secondary side, or an asymmetric half bridge circuit. The NCP1282 reduces component count and system size by incorporating high accuracy on critical specifications such as maximum duty cycle limit, undervoltage detector and overcurrent threshold. Two distinctive features of the NCP1282 are soft-stop and a cycle skip current limit with a time threshold. Soft-stop circuitry powers down the converter in a controlled manner if a severe fault is detected. The cycle skip detector enables a soft-stop sequence if a continuous overcurrent condition is present. Additional features found in the NCP1282 include line feed- forward, frequency synchronization up to 1.0 MHz, cycle-by-cycle current limit with leading edge blanking (LEB), independent under and overvoltage detectors, adjustable output overlap delay, programmable maximum duty cycle, internal startup circuit and soft-start.
http://onsemi.com MARKING DIAGRAM
SO-16 D SUFFIX CASE 751B NCP1282BG AWLYWW
A WL, L Y WW, W G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
ORDERING INFORMATION
Device NCP1282BDR2G Package SO-16 (Pb-Free) Shipping 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Features
* Dual Control Outputs with Adjustable Overlap Delay * >2.0 A Output Drive Capability * Soft-Stop Powers Down Converter in a Controlled
Manner
* Minimum Operating Voltage of 8.5 V Ensures Enough * * * * * * * * * *
* Cycle-by-Cycle Current Limit * Cycle Skip Initiated if Continuous Current Limit
Condition Exists
* Voltage Mode Operation with Input Voltage * * *
Feedforward Fixed Frequency Operation up to 1.0 MHz Bidirectional Frequency Synchronization Independent Line Undervoltage and Overvoltage Detectors
Voltage is Available for Driving High Voltage MOSFETs Accurate Programmable Maximum Duty Cycle Limit Programmable Maximum Volt-Second Product Programmable Soft-Start Internal 500 V Startup Circuit Precision 5.0 V Reference This is a Pb-Free Device* High Power Consumer Electronics High Power AC-DC Converters High Power DC-DC Converters ATX Power Supplies
Typical Applications
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
December, 2006 - Rev. 0
1
Publication Order Number: NCP1282/D
NCP1282
1 Vin 16 CAUX VAUX + - VAUX(on)/ VAUX(off1)/ VAUX(off2) Iinhibit Istart Disable VAUX(on) P.O.R. Bias Disable_VREF S Dominant Reset Q Latch R VAUX 8 5.0 V Reference VREF
- +
+ -
- +
1V
One Shot Pulse
Central Logic Thermal Shutdown
Vin R1 R2 2 UVOV UVOV Detector
VUV
Soft-Stop Complete Enable_Output VAUX 15 OUT1
STOP
Vref RT 3V 6 RTCT 7 SYNC 12 CCSKIP CSKIP ICSKIP(D) + - 4 CS Soft-Stop Complete VREF 10 CSS SS ISS(D) Clock Fixed 80 ns LEB Enable Soft-Start Soft-Stop Control Logic 0.5 V OUT Not Saturated ICSKIP(C) VREF CSKIP Control Logic + - 500 mA Oscillator DMAX SYNC Clock
Clock
CSKIP Comparator
S Q Dominant Reset Latch Q R Saturation Comparator
14 Delay Logic VAUX 13 OUT2 11 tD 3.6 V VREF 20 kW 9 VX VEA 270 kW RD PGND
2V CT
+ -
VCSKIP
FF Reset
+ -
Not Saturated
+ -
- +
Clock Ilimit Comparator
- +
PWM Comparator Soft-Start Comparator
-+
Vin FF Comparator +
-+
0.2 V -
RFF 3 FF CFF
ISS(C)
STOP VX Soft-Start Complete
+ 3V -
Enable_Output
FF Reset
5 GND
Figure 1. Detailed Block Diagram
http://onsemi.com
2
NCP1282
PIN FUNCTION DESCRIPTION
Pin 1 Symbol Vin Description Connect the input line voltage directly to this pin to enable the internal startup regulator. A constant current source supplies current from this pin to the capacitor connected to the VAUX pin, eliminating the need for a startup resistor. The charge current is typically 10 mA. Maximum input voltage is 500 V. Input supply voltage is scaled down and sampled by means of a resistor divider. The same pin is used for both undervoltage (UV) and overvoltage (OV) detection using a novel architecture (patent pending). The minimum and maximum input supply voltage thresholds are adjusted independently. A UV condition exists if the UVOV voltage is below 2.0 V and an OV condition exists if the UVOV voltage exceeds 3.0 V. The undervoltage threshold is trimmed during manufacturing to obtain "3% accuracy allowing a tighter power stage design. Both the UV and OV detectors have a 100 mV hysteresis. An external R-C divider from the input line generates the Feedforward Ramp. This ramp is used by the PWM comparator to set the duty cycle, thus providing direct line regulation. An internal pulldown transistor discharges the external capacitor every cycle. Once discharged, the capacitor is effectively grounded until the next cycle begins. Overcurrent sense input. If the CS voltage exceeds 0.5 V the converter operates in cycle-by-cycle current limit. Once a current limit pulse is detected, the cycle skip timer is enabled. Internal leading edge blanking pulse prevents nuisance triggering during normal operation. The leading edge blanking is disabled during soft-start and output overload conditions to improve the response to faults. Control circuit ground. All control and timing components that connect to GND should have the shortest loop possible to this pin to improve noise immunity. An external RT-CT divider from VREF sets the operating frequency and maximum duty cycle of OUT1. The maximum operating frequency is 1.0 MHz. A sawtooth Ramp between 2.0 V and 3.0 V is generated by sequentially charging and discharging CT. The peak and valley of the Ramp are accurately controlled to provide precise control of the duty cycle and frequency. The outputs are disabled during the CT discharge time. Proprietary bidirectional frequency synchronization architecture allows two NCP1282 devices to synchronize together. The lower frequency device becomes the slave. It can also synchronize to an external signal. Precision 5.0 V reference. Maximum output current is 5.0 mA. It is required to bypass the reference with a capacitor. The recommended capacitance range is between 0.047 mF and 1.0 mF. The error signal from an external error amplifier is fed to this input and compared to the Feedforward Ramp. A series diode and resistor offset the voltage on this pin before it is applied to the PWM Comparator inverting input. An internal pullup resistor allows direct connection to an optocoupler. A 20 mA current source charges the external capacitor connected to this pin. Duty cycle is limited during startup by comparing the voltage on this pin to the Feedforward Ramp. Under steady state conditions, the SS voltage is approximately 3.8 V. Once a UV, OV, low VAUX, overtemperature or cycle skip fault is detected, the SS capacitor is discharged in a controlled manner with a 100 mA current source. The duty cycle is then slowly reduced until reaching 0%. An external resistor between this pin and GND sets the overlap time delay between OUT1 and OUT2 transitions. The converter is disabled if a continuous overcurrent condition exists. The time to determine the fault and the time the converter is disabled are programmed by the capacitor (CCSKIP) connected to this pin. The cycle skip timer is enabled after a current limit fault is detected. Once enabled, CCSKIP is charged with a 100 mA source. If the overcurrent fault is removed before entering the soft-stop mode, the capacitor is discharged with a 10 mA source. Once CCSKIP reaches 3.0 V, the converter enters a soft-stop mode and CCSKIP is discharged with a 10 mA source. The converter is re-enabled once CCSKIP reaches 0.5 V. If the condition resulting in overcurrent is cleared during this phase, CCSKIP discharges to 0 V. Otherwise, it starts charging from 0.5 V, setting up a hiccup mode operation. Secondary output of the PWM Controller. It can be used to drive an active clamp/reset switch, a synchronous rectifier topology, or both. OUT2 has an adjustable leading and trailing edge overlap delay against OUT1. OUT2 has source and sink resistances of 12 W (typ.). OUT2 is designed to handle up to 1.0 A. Ground connection for OUT1 and OUT2. Tie to the power stage return with a short loop. Main output of the PWM Controller. OUT1 has a source resistance of 4.0 W (typ.) and a sink resistance of 2.5 W (typ.). OUT1 is designed to handle up to 2.5 A. OUT1 trails OUT2 during a low to high transition and leads OUT2 during a high to low transition. Positive input supply. This pin connects to an external capacitor for energy storage. An internal current source supplies current from Vin to this pin. Once the voltage on VAUX reaches approximately 11.0 V, the current source turns OFF and the outputs are enabled. Once VAUX reaches 9.5 V the startup circuit is enabled and the controller enters the soft-stop mode. The outputs are immediately disabled if VAUX reaches 8.5 V. During normal operation, power is supplied to the IC via this pin by means of an auxiliary winding. The startup circuit is disabled once the voltage on the VAUX pin exceeds 11.0 V. If the VAUX voltage drops below 1.2 V (typ), the startup current is reduced to 200 mA.
2
UVOV
3
FF
4
CS
5 6
GND RTCT
7
SYNC
8 9
VREF VEA
10
SS
11 12
tD CSKIP
13
OUT2
14 15
PGND OUT1
16
VAUX
http://onsemi.com
3
NCP1282
MAXIMUM RATINGS (Notes 1 and 2)
Rating Line Voltage Auxiliary Supply, OUT1, OUT2 All Other Inputs/Outputs Voltage All Other Inputs/Outputs Current 5.0 V Reference Output Current 5.0 V Reference Output Voltage OUT1 Peak Output Current (D = 2%) OUT2 Peak Output Current (D = 2%) Operating Junction Temperature Storage Temperature Range Power Dissipation (TA = 25C, 2.0 Oz Cu, 1.0 Sq Inch Printed Circuit Copper Clad) D Suffix, Plastic Package Case 751B (SO-16) Thermal Resistance, Junction to Ambient (2.0 Oz Cu Printed Circuit Copper Clad) D Suffix, Plastic Package Case 751B (SO-16) 0.36 Sq In 1.0 Sq In Symbol Vin VAUX, Voutx VIO IIO IREF VREF Iout1 Iout2 TJ Tstg PD RqJA 120 105 Value 500 20 10 5.0 10 -0.3 to 6.0 2.5 1.0 -40 to +125 -55 to +150 0.95 Unit V V V mA mA V A A C C W C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: Pins 2-16: Human Body Model 2000 V per MIL-STD-883, Method 3015. Machine Model Method 160 V. Pin 1 is the HV startup of the device and is rated to the max rating of the part, or 500 V. 2. This device contains Latchup protection and exceeds "100 mA per JEDEC Standard JESD78.
http://onsemi.com
4
NCP1282
ELECTRICAL CHARACTERISTICS (Vin = 48 V, VAUX = 12 V, VUVOV = 2.3 V, VEA = open, VCSKIP = 0 V, VCS = 0 V, VSS = open, RT = 13.3 kW, CAUX = 10 mF, CT = 470 pF, Cout1 = Cout2 = 100 pF, CUVOV = 0.01 mF, CCSKIP = 6800 pF, RD = 25 kW, RSYNC = 5.0 kW, CREF = 0.1 mF, RFF = 29.4 kW, CFF = 470 pF. For typical values TJ = 25C, for min/max values, TJ is - 40C to 125C, unless otherwise noted.)
Characteristic STARTUP CONTROL AND VAUX REGULATOR VAUX Regulation (VUVOV = 0 V) Inhibit Threshold Voltage Startup Threshold/VAUX Regulation Peak (VAUX Increasing) Operating VAUX Valley Voltage Minimum Operating VAUX Valley Voltage after Turn-On (VUVOV = 2.3 V, VEA = 0 V) Minimum Startup Voltage (Pin 1) IAUX = 1.0 mA, VAUX = VAUX(on) - 0.2 V Inhibit Bias Current VAUX = 0 V Startup Circuit Output Current VAUX = Vinhibit + 0.2 V VAUX = VAUX(on) - 0.2 V Startup Circuit Off-State Leakage Current (Vin = 500 V, VUVOV = 0 V) TJ = 25C TJ = -40C to 125C Startup Circuit Breakdown Voltage (Note 3) Istart(off) = 50 mA, TJ = 125C Auxiliary Supply Current after VAUX Turn-On Outputs Disabled VUVOV = 0 V VEA = 0 V Outputs Enabled VEA = 4.0 V LINE UNDER/OVERVOLTAGE DETECTOR Undervoltage Threshold (Vin Increasing) Undervoltage Hysteresis Undervoltage Ratio (VUV(H)/VUV) Overvoltage Threshold (Vin Increasing) Overvoltage Hysteresis Offset Current (VUVOV = 2.8 V) Offset Current Turn ON Threshold ("5%, Ioffset(UVOV) = 40 mA) LINE FEEDFORWARD Peak Voltage (Volt-Second Clamp) Discharge Current (VFF = 0.5 V, VSS = 0 V) Offset Voltage (VFF = 0 V, Ramp Down VSS) Feedforward Offset Minus Soft-Stop Reset Voltage 3. Guaranteed by design only. VFF(peak) IFF(D) Voffset(FF) D(FF-SS) 2.8 8.5 0.118 7 3.0 - 0.185 70 3.2 - 0.268 183 V mA V mV VUV VUV(H) VUV(ratio) VOV VOV(H) Ioffset(UVOV) Voffset(UVOV) 1.979 0.074 3.65 2.80 0.075 38 2.4 2.05 0.093 4.5 2.95 0.093 48 2.6 2.116 0.118 5.62 3.10 0.127 58 2.8 V V % V V mA V Vinhibit VAUX(on) VAUX(off1) VAUX(off2) Vstart(min) - 10.6 8.9 8.0 1.15 11.1 9.4 8.4 1.6 11.6 9.9 9.0 V Symbol Min Typ Max Unit
- 70 7.16 4.03 - - 500
- 171 9.3 6.1 25 - -
23.2 270 11.3 8.1 50 100 -
V mA mA
Iinhibit Istart1 Istart2 Istart(off)
mA
VBR(DS)
V mA
IAUX1 IAUX2 IAUX3
- - -
3.1 4.3 4.9
3.6 4.94 7.0
http://onsemi.com
5
NCP1282
VCS = 0 V, VSS = open, RT = 13.7 kW, CAUX = 10 mF, CT = 470 pF, Cout1 = Cout2 = 100 pF, CUVOV = 0.01 mF, CCSKIP = 6800 pF, RD = 25 kW, RSYNC = 5.0 kW, CREF = 0.1 mF, RFF = 29.4 kW, CFF = 470 pF. For typical values TJ = 25C, for min/max values, TJ is - 40C to 125C, unless otherwise noted) Characteristic CURRENT LIMIT AND THERMAL SHUTDOWN Cycle-by-Cycle Threshold Voltage (Vout = 10 V) Propagation Delay to Output (VCS = VILIM to 1.0 V, LEB Disabled, Vout = 10 V) TJ = 25C TJ = -40C to 125C Thermal Shutdown Threshold (Junction Temperature Increasing, Note 4) Thermal Shutdown Hysteresis (Temperature Decreasing, Note 4) LEADING EDGE BLANKING Offset Voltage Blanking Time VEA Threshold that Disables LEB (Measured together with tLEB) CYCLE SKIP CURRENT LIMIT MODE Charge Current (VCSKIP = 1.25 V) Discharge Current (VCSKIP = 1.25 V) Number of Pulses to Exit Cycle Skip Mode Upper Threshold Voltage (Ramp up VCSKIP, VCS = 1.0 V) Lower Threshold Voltage (Ramp down VCSKIP) Threshold Voltage Hysteresis 5.0 V REFERENCE Output Voltage (IREF = 0 mA) Load Regulation (IREF = 0 to 5.0 mA) Line Regulation (VAUX = 10.5 to 20 V, IREF = 0 mA) Discharge Current (VUVOV = 0 V, VREF = 2.5 V) OSCILLATOR Frequency TJ = 25C ("5%) TJ = -40C to 125C ("7.5%) Peak Voltage ("3%) Valley Voltage ("3%) Discharge Current (VRTCT = 2.3 V) Maximum Operating Frequency (Note 4) Duty Cycle (RD = 25 kW) Adjustable Maximum Duty Cycle (Note 4) 4. Guaranteed by design only. fOSC 222 211.2 VRTCT(peak) VRTCT(valley) IRTCT fMAX D DMAX - - - 1.0 58.8 85 246 - 2.92 2.1 480 - 62.6 - 272.2 277.2 - - - - 65 - V V mA MHz % % kHz VREF VREF(Load) VREF(line) IREF(D) 4.875 - - 3.8 5.0 16 8.0 - 5.075 50 50 - V mV mV mA ICSKIP(C) ICSKIP(D) PulseCSKIP VCSKIP(peak) VCSKIP(valley) VCSKIP(H) 66 6.5 - 2.83 0.39 - 90 8.6 3 3.03 0.465 2.5 111 11 - 3.24 0.52 - mA mA - V V V VLEB(offset) tLEB VLEB(dis) - 65 4.1 10 75 - - 116 - mV ns V VILIM tILIM - - TSHDN TH - - 80 - 160 25 90 110 - - C C 476 495 512 mV ns Symbol Min Typ Max Unit
ELECTRICAL CHARACTERISTICS (continued) (Vin = 48 V, VAUX = 12 V, VUVOV = 2.3 V, VEA = open, VCSKIP = 0 V,
http://onsemi.com
6
NCP1282
VCS = 0 V, VSS = open, RT = 13.7 kW, CAUX = 10 mF, CT = 470 pF, Cout1 = Cout2 = 100 pF, CUVOV = 0.01 mF, CCSKIP = 6800 pF, RD = 25 kW, RSYNC = 5.0 kW, CREF = 0.1 mF, RFF = 29.4 kW, CFF = 470 pF. For typical values TJ = 25C, for min/max values, TJ is - 40C to 125C, unless otherwise noted.) Characteristic SYNCHRONIZATION Output Pulse Width Output Voltage High (RSYNC = R) Sync Threshold Voltage (Note 5) Sync Input Pulse Width (VSYNC = 3.5 V) Maximum Sync Frequency (Note 5) Source Current (Note 5) SOFT-START/STOP Charge Current (VSS = 1.6 V) Discharge Current (VUVOV = 0 V, VSS = 1.6 V) Soft-Stop Reset Voltage (VFF = 0 V) OUTPUTS Overlap Time Delay (Tested at 50% of Waveform) RD = 25 kW Leading Trailing Output Voltage (IOUT = 0 mA, Note 5) Low State High State Drive Resistance (FT ONLY) OUT1 Sink (VRTCT = 4.0 V, Vout1 = 1 V) TJ = 25C TJ = -40C to 125C OUT1 Source (VRTCT = 2.5 V, Vout1 = 11 V) TJ = 25C TJ = -40C to 125C OUT2 Sink (VRTCT = 4.0 V, Vout2 = 1 V) TJ = 25C TJ = -40C to 125C OUT2 Source (VRTCT = 2.5 V, Vout2 = 11 V) TJ = 25C TJ = -40C to 125C Rise Time (10% to 90%, Cout1 = 2200 pF, Cout2 = 220 pF) OUT1 OUT2 Fall Time (90% to 10%, Cout1 = 2200 pF, Cout2 = 220 pF) OUT1 OUT2 PWM COMPARATOR Input Resistance Lower Input Threshold Delay to Output (From VOH to 0.5 VOH) 5. Guaranteed by design only. RIN(VEA) VEA(L) tPWM 14 0.48 - 26 0.84 100 50 1.04 - kW V ns ns tD(leading) tD(trailing) VOL VOH RSNK1 - - RSRC1 - - RSNK2 - - RSRC2 - - tr1 tr2 tf1 tf2 - - - - 11.8 - 26 19 10 10 13.5 20 ns - - ns - - 11.6 - 12.7 20.0 4.6 - 5.75 7.45 2.9 - 3.6 5.03 37 72 - 11.8 53 99 - - - - V 0.25 - W ISS(C) ISS(D) Vreset(SS) 15 70 - 20 100 115 30 130 - mA mA mV tO(SYNC) VH(SYNC) VSYNC tSYNC fSYNC ISYNC(D) 70 - 3.5 - - - 122 4.3 - - - 1.0 - - - tO(SYNC)min 1.0 - ns V V ns MHz mA Symbol Min Typ Max Unit
ELECTRICAL CHARACTERISTICS (continued) (Vin = 48 V, VAUX = 12 V, VUVOV = 2.3 V, VEA = open, VCSKIP = 0 V,
http://onsemi.com
7
NCP1282
Vinhibit, INHIBIT THRESHOLD VOLTAGE (V) VAUX, AUXILIARY SUPPLY VOLTAGE (V) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 -50 -25 0 25 50 75 100 125 150 VAUX(off2) VAUX(off1) VAUX(on)
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 2. Startup Circuit Inhibit Voltage Threshold vs. Junction Temperature
Figure 3. Auxiliary Supply Voltage Thresholds vs. Junction Temperature
12 Istart, STARTUP CURRENT (mA) Istart, STARTUP CURRENT (mA) 11 10 9 8 7 6 5 4 3 2 -50 VAUX = VAUX(on) - 0.2 V VAUX = Vinhibit + 0.2 V Vin = 48 V
10 9 8 7 6 5 4 3 2 1 0 Vin = 48 V TJ = 25C
-25
0
25
50
75
100
125
150
0
2
4
6
8
10
12
TJ, JUNCTION TEMPERATURE (C)
VAUX, SUPPLY VOLTAGE (V)
Figure 4. Startup Current vs. Junction Temperature
100 90 80 70 60 50 40 30 20 10 0 0 50 VAUX = 12 V
Figure 5. Startup Current vs. Supply Voltage
Istart(off), STARTUP CIRCUIT LEAKAGE CURRENT (mA)
TJ = -40C TJ = 25C TJ = 125C 100 150 200 250 300 350 400 Vin, INPUT VOLTAGE (V) 450 500
Figure 6. Startup Circuit Leakage Current vs. Input Voltage
http://onsemi.com
8
NCP1282
IAUX, AUXILIARY SUPPLY CURRENT (mA) IAUX3, POWER SUPPLY CURRENT (mA) 10 9 8 7 6 5 4 3 2 1 0 -50 VUVOV = 0 V VUVOV = 2.3 V, Cout1 = Cout2 = 100 pF VUVOV = 2.3 V, VEA = 0 V VAUX = 12 V 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 10 11 12 13 14 15 Vin = 48 V TJ = 25C fOSC [ 230 kHz Cout1 = Cout2 = 100 pF 16 17 18 19 20
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
VAUX, POWER SUPPLY VOLTAGE (V)
Figure 7. Auxiliary Supply Current vs. Junction Temperature
VUV/OV, LINE UNDER/OVERVOLTAGE THRESHOLDS (V) VUV/OV(H), UNDER/OVERVOLTAGE HYSTERESIS (mV)
Figure 8. Supply Current vs. Supply Voltage
3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 -50 UNDERVOLTAGE -25 0 25 50 75 100 125 150 OVERVOLTAGE
150 140 130 120 110 100 90 80 70 60 50 -50 UNDERVOLTAGE OVERVOLTAGE
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 9. Line Under/Overvoltage Thresholds vs. Junction Temperature
75 IFF(D), DISCHARGE CURRENT (mA) 70 65 60 55 50 45 40 35 30 25 -50 VAUX = 12 V VUVOV = 2.8 V 50 45 40 35 30 25 20 15 10 5 0 -50
Figure 10. Line Under/Overvoltage Hysteresis vs. Junction Temperature
Ioffset(UVOV), UVOV OFFSET CURRENT (mA)
VCC = 12 V VSS = 0 V VFF = 0.5 V
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 11. UVOV Offset Current vs. Junction Temperature
Figure 12. FF Discharge Current vs. Junction Temperature
http://onsemi.com
9
NCP1282
250 Voffset(FF)/Vreset(SS), FF OFFSET AND SS RESET VOLTAGES (mV) FF-Offset VFF(peak), FF PEAK VOLTAGE (V) 75 100 125 150 225 200 175 150 125 100 75 50 25 0 -50 SS Reset 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 -50
-25
0
25
50
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 13. FF Offset and SS Reset Voltages vs. Junction Temperature
VILIM, CURRENT LIMIT THRESHOLD VOLTAGE (mV) tILIM, CURRENT LIMIT PROPAGATION DELAY (ns)
Figure 14. Feedforward Peak Voltage vs. Junction Temperature
550 540 530 520 510 500 490 480 470 460 450 -50
150 140 130 120 110 100 90 80 70 60 50 -50
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 15. Current Limit Threshold Voltage vs. Junction Temperature
Figure 16. Current Limit Propagation Delay vs. Junction Temperature
100 90 80 tLEB, LEB TIME (ns) 70 60 50 40 30 20 10 0 -50
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
Figure 17. Leading Edge Blanking Time vs. Junction Temperature
http://onsemi.com
10
NCP1282
ICSKIP(D), CYCLE SKIP DISCHARGE CURRENT (mA) ICSKIP(C), CYCLE SKIP CHARGE CURRENT (mA)
150 140 130 120 110 100 90 80 70 60 50 -50 VCSKIP = 1.25 V
15 14 13 12 11 10 9 8 7 6 5 -50 -25 0 25 50 75 100 125 150 VCSKIP = 1.25 V
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 18. Cycle Skip Charge Current vs. Junction Temperature
3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 -50 LOWER THRESHOLD UPPER THRESHOLD 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 -25 0 25 50 75 100 125 0 150 5.25 5.20 5.15 5.10 5.05 5.00 4.95 4.90 4.85 4.80 4.75 -50
Figure 19. Cycle Skip Discharge Current vs. Junction Temperature
VCSKIP(valley), LOWER THRESHOLD (V) VREF, REFERENCE VOLTAGE (V)
VCSKIP(peak), UPPER THRESHOLD (V)
VAUX = 12 V
VREF = 0 mA VREF = 5 mA
-25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 20. Cycle Skip Voltage Thresholds vs. Junction Temperature
IREF(D), VREF DISCHARGE CURRENT (mA) 10 9 8 7 6 5 4 3 2 1 0 -50 VCC = 12 V VUVOV = 0 V VREF = 2.5 V -25 0 25 50 75 100 125 150 750 700 650 600 550 500 450 400 350 300 250 200 -50
Figure 21. Reference Voltage vs. Junction Temperature
fOSC, OSCILLATOR FREQUENCY (kHz)
CT = 150 pF
VAUX = 12 V RT = 14 kW RD = 69.8 kW
CT = 220 pF
CT = 470 pF -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 22. VREF Discharge Current vs. Junction Temperature
Figure 23. Oscillator Frequency vs. Junction Temperature
http://onsemi.com
11
NCP1282
fOSC, OSCILLATOR FREQUENCY (kHz) 900 800 700 600 500 400 300 200 100 0 10 CT = 470 pF 30 50 70 90 RT, TIMING RESISTOR (kW) 110 CT = 220 pF CT = 150 pF VAUX = 12 V TJ = 25C D, DUTY CYCLE (%) 90 85 80 75 70 65 60 55 50 45 40 10 30 50 70 VAUX = 12 V TJ = 25C RD = 69.8 kW 90 110 RT, TIMING RESISTOR (kW ) CT = 150 pF CT = 220 pF CT = 470 pF
Figure 24. Oscillator Frequency vs. Timing Resistor
Figure 25. Duty Cycle vs. Timing Resistor
90 ISS(C), CHARGE CURRENT (mA) 85 D, DUTY CYCLE (%) 80 75 70 65 60 55 50 45 40 -50 -25 0 25 50 75 100 125 150 RT = 20 kW, CT = 150 pF RT = 15.8 kW, CT = 220 pF RT = 11.8 kW, CT = 470 pF VAUX = 12 V RD = 69.8 kW
25 24 23 22 21 20 19 18 17 16 15 -50 DISCHARGE (VUVOV = 0 V) CHARGE VAUX = 12 V
150 140 130 120 110 100 90 80 70 60 50 150 ISS(D), DISCHARGE CURRENT (mA)
-25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 26. Duty Cycle vs. Junction Temperature
Figure 27. Soft-Start/Stop Charge and Discharge Currents vs. Junction Temperature
500 tD, OVERLAP TIME DELAY (ns) 400 350 300 250 200 150 100 50 0 VAUX = 12 V TJ = 25C 0 80 160 240 320 RD, DELAY RESISTOR (kW) 400 LEADING TRAILING tD, OVERLAP TIME DELAY (ns) 450
400 350 300 250 200 150 100 50 0 -50 -25
tD(trail)
VAUX = 12 V RD = 200 kW
tD(lead)
tD(trail) tD(lead) tD(trail) tD(lead) 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 RD = 69.8 kW
RD = 20 kW
Figure 28. Overlap Time Delay vs. Delay Resistor
Figure 29. Overlap Time Delay vs. Junction Temperature
http://onsemi.com
12
NCP1282
RSNK/SRC, OUTPUT 1 DRIVE RESISTANCE (W) 10 9 8 7 6 5 4 3 2 1 0 -50 SINK, Vout1 = 1 V -25 0 25 50 75 100 125 150 SOURCE, Vout1 = 11 V VAUX = 12 V RSNK/SRC, OUTPUT 2 DRIVE RESISTANCE (W)
18 17 16
VAUX = 12 V
15 14 13 SOURCE, Vout2 = 11 V 12 11 10 9 8 7 6 -50 SINK, Vout2 = 1 V
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 30. Output 1 Drive Resistance vs. Junction Temperature
Figure 31. Output 2 Drive Resistance vs. Junction Temperature
RIN(VEA), VEA INPUT RESISTANCE (kW)
50 VEA(L), PWM COMPARATOR LOWER INPUT THRESHOLD (V) 45 40 35 30 25 20 15 10 5 0 -50 -25 0 25 50 75 100 125 150 VEA = 0 V
1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 -50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 32. VEA Input Resistance vs. Junction Temperature
Figure 33. PWM Comparator Lower Input Threshold vs. Junction Temperature
http://onsemi.com
13
NCP1282
DETAILED OPERATING DESCRIPTION The NCP1282 is a voltage mode controller designed for ac-dc or dc-dc converters requiring high-efficiency and low parts count. This controller incorporates two in phase outputs with an adjustable overlap delay. The main output is designed for driving a forward converter primary MOSFET. The secondary output is designed for driving an active clamp circuit MOSFET, a synchronous rectifier on the secondary side, or an asymmetric half bridge circuit. Two distinctive features of the NCP1282 are the soft-stop and a cycle skip overcurrent detector with a time threshold. The soft-stop powers down the converter in a controlled manner after a fault is detected. The cycle skip timer disables the converter if a continuous overcurrent condition is present. The NCP1282 reduces component count and system size by incorporating high accuracy on critical specifications such as programmable maximum duty cycle, undervoltage detector and overcurrent threshold. A minimum operating voltage of 8.5 V ensures enough voltage is available for driving high voltage MOSFETs. Additional features found in the NCP1282 include line feedforward, bidirectional frequency synchronization up to 1.0 MHz, cycle-by-cycle current limit with leading edge blanking (LEB), independent under and overvoltage detectors, internal startup circuit and soft-start. SOFT-STOP AND SOFT-START The NCP1282 incorporates a novel soft-stop and soft-start architecture that combines soft-start and soft-stop functions on a single pin. Soft-stop reduces the duty cycle until it reaches 0% once a fault is detected. By slowly reducing the duty cycle during power down, the active clamp capacitor (Cclamp) is discharged. This prevents oscillations between the power transformer and Cclamp, and ensures the converter turns off in a predictable state. Soft-start slowly increases the duty cycle during power up allowing the controller to gradually reach steady state operation. Combined, both features reduce system stress and power surges. The duty cycle is controlled by comparing the SS capacitor voltage (VSS) to the Feedforward (FF) Ramp. Soft-start or soft-stop is implemented by slowly charging or discharging the capacitor on the SS pin. OUT1 is disabled once the FF Ramp exceeds VSS. The soft-start charge current is 20 mA and the soft-stop discharge current is 100 mA, guaranteeing a faster turn OFF time. The preset 1:5 charge:discharge ratio can be reduced by placing an external resistor between the VREF and SS pins. The resistor should be sized such that the total charge current does not exceed 100 mA. Otherwise, the converter will not be able to complete a soft-stop sequence. The converter enters a soft-stop sequence if an undervoltage, overvoltage, cycle skip low VAUX (VAUX(off1)) or thermal shutdown condition is detected. Once the converter enters the soft-stop mode, it will stay in soft-stop mode until VSS reaches 0.2 V even if the fault is removed prior to reaching 0.2 V. Depending on the converter state, a soft-stop sequence is handled differently to ensure the fastest response time and prevent system malfunction. If a soft-stop sequence starts before VSS exceeds the maximum voltage clamp of the FF Ramp (typ. 3.0 V) and the PWM Comparator (VEA) is not yet controlling the duty cycle, a controlled discharge of CSS commences immediately, as shown in Figure 34. However, if VEA is controlling the duty cycle, CSS is discharged until soft-stop sets a duty cycle equal to the duty cycle set by VEA. A controlled discharge commences afterwards, as shown in Figure 35. If VSS exceeds the FF Ramp and the VEA is not controlling the duty cycle, VSS is forced to the peak voltage of the FF Ramp, before starting a controlled discharge of CSS, as shown in Figure 36. The duty cycle set at the beginning of the soft-stop event never exceeds the duty cycle prior to the soft-stop event.
(VEA is not controlling the duty cycle) VEA
VSS FF Ramp
Figure 34. Soft-Stop Before Soft-Start is Complete and VEA is Open.
VSS VEA VX = VEA - Vf
Figure 35. Soft-Stop Behavior when VEA Controls the Duty Cycle.
http://onsemi.com
14
NCP1282
Cycle Skip
(VEA is not controlling the duty cycle) VEA VSS FF Ramp
Figure 36. Soft-Stop Behavior After Soft-Start is Complete and VEA is Open.
If the voltage on the VAUX pin reaches VAUX(off2), CSS is immediately discharged and the outputs are disabled. VSS should not be pulled up or down externally. CURRENT LIMIT The NCP1282 has two overcurrent modes, cycle-by-cycle and cycle skip, providing the best protection during momentary and continuous overcurrent conditions.
Cycle-by-Cycle
In cycle-by-cycle, the conduction period ends once the voltage on the CS pin reaches the current limit voltage threshold (VILIM). The NCP1282 has a VILIM of 0.5 V.
Traditionally, a voltage on the CS higher than VILIM has been used to trigger a cycle skip fault. Unfortunately, the fast response time of modern controllers makes it hard to reach a voltage on the CS pin higher than VILIM. Instead of using a higher voltage threshold to detect a cycle skip fault, the NCP1282 uses a timer. It monitors the current limit comparator and if a continuous cycle-by-cycle current limit condition exists the converter is disabled. The time to disable the converter and the time the converter is disabled are programmed by the capacitor on the CSKIP pin, CCSKIP. The cycle skip detection circuit charges CCSKIP with a continuous 100 mA current once cycle-by-cycle current limit fault is detected. If the current limit fault persists, CCSKIP continues to charge until reaching the cycle skip upper threshold (VCSKIP(peak)) of 3.0 V. Once reached, the converter enters the soft-stop mode and CCSKIP is discharged with a constant 10 mA current. A new soft-start sequence commences once CCSKIP reaches the lower cycle skip threshold (VCSKIP(valley)) of 0.5 V. If the overcurrent condition is still present, the capacitor starts charging on the next current limit event. Otherwise, CCSKIP is discharged down to 0 V. The cycle skip capacitor provides a means of remembering previous overcurrent conditions. If a continuous overcurrent condition is removed before reaching VCSKIP(peak), CCSKIP starts a controlled discharge. If the continuous overcurrent fault is once again detected before CCSKIP is completely discharged, CCSKIP charges from its existing voltage level, taking less time to reach VCSKIP(peak). Figure 37 shows operating waveforms during a continuous overcurrent condition. For optimal operation, the cycle skip discharge time should be longer than the soft-stop period.
VILIM CS
VCSKIP(peak) VCSKIP VCSKIP(valley)
VSS
Figure 37. Cycle Skip Waveforms
In some instances it may be desired to latch (instead of auto re-start) the NCP1282 after a cycle skip event is detected. This can be easily achieved by adding an external latch.
Figures 35 and 36 show an implementation of an integrated and a discrete latch, respectively. In general the circuits work by pulling CSKIP to VREF, preventing it from reaching
http://onsemi.com
15
NCP1282
VCSKIP(valley) once the CSKIP voltage reaches the turn on threshold of the latch. The external latch is cleared by bringing the UVOV voltage below VUV and disabling VREF.
VREF CREF OUTY VCC INA
CSKIP CCSKIP
OE
MC74VHC1GT126
is usually filtered using an RC low-pass filter to avoid premature triggering of the current limit circuit. However, the low pass filter will inevitably change the shape of the current pulse and also add cost and complexity. The NCP1282 uses LEB circuitry that blocks out the first 70 ns (typ) of each current pulse. This removes the leading edge spikes without altering the current waveform. The blanking period is disabled during soft-start as the blanking period may be longer than the startup duty cycle. It is also disabled if the output of the Saturation Comparator is low, indicating that the output is not yet in regulation. This occurs during power up or during an output overload condition.
Supply Voltage and Startup Circuit
Figure 38. External Latch Implemented using ON Semiconductor's MiniGatet Buffer
The latch in Figure 38 consists of a TTL level tri-state output buffer from ON Semiconductor's MiniGatet family. The enable (OE) and output (OUTY) terminals are connected to CSKIP and the VCC and INA pins are connected to VREF. The output of the buffer is in a high impedance mode when OE is low. Once a continuous current limit condition is detected, the CSKIP timer is enabled and CSKIP begins charging. Once the voltage on CSKIP reaches the enable threshold of the buffer, the output of the buffer is pulled to VREF, latching the CSKIP timer. The OE threshold of the buffer is typically 1.5 V.
VREF CREF BSS84L M2 CSKIP CCSKIP M1 2N7002L 24.9 kW Rpull-up
Figure 39. External Latch Implemented using Discrete N and P-Channel MOSFETs
A latch implemented using discrete N and P-channel MOSFETs is shown in Figure 39. The latch is enabled once the CSKIP voltage reaches the threshold of M1. Once M1 turns on, it pulls low the gate of M2. CSKIP is then pulled to VREF by M2. It is important to size Rpull-up correctly. If Rpull-up is too big, it will not keep M2 off while VREF charges. This will cause the controller to latch during initial power-up. In this particular implementation the turn on threshold of M1 is 2 V and Rpull-up is sized to 24.9 k.
Leading Edge Blanking
The current sense signal is prone to leading edge spikes caused by the power switch transitions. The current signal
The NCP1282 internal startup regulator eliminates the need for external startup components. In addition, this regulator increases the efficiency of the supply as it uses no power when in the normal mode of operation, but instead uses power supplied by an auxiliary winding. The NCP1282 incorporates an optimized startup circuit that reduces the requirement of the supply capacitor, particularly important in size constrained applications. The minimum supply voltage of the NCP1282 is optimized for driving high voltage MOSFETs. It is not uncommon for high voltage MOSFETs to have a gate plateau voltage of 6 V. In addition, high voltage applications may require a high side drive circuit with a voltage drop of up to two diodes. If the minimum supply voltage is too low, there may not be enough voltage for driving the external MOSFETs causing the system to malfunction. The NCP1282 eliminates this problem with a minimum supply voltage of 8.5 V. The startup regulator consists of a constant current source that supplies current from the input line voltage (Vin) to the supply capacitor on the VAUX pin (CAUX). The startup current (Istart) is typically 10 mA. Once CAUX is charged to 11.0 V (VAUX(on)), the startup regulator is disabled and the outputs are enabled if there are no UV, OV, CSKIP or thermal shutdown faults. The startup regulator remains disabled until the lower voltage threshold (VAUX(off1)) of 9.5 V is reached. Once reached, the startup circuit is enabled and a soft-stop event is initiated. If the bias current requirement out of CAUX is greater than the startup current, VAUX will discharge until reaching the lower voltage threshold (VAUX(off2)) of 8.5 V. Upon reaching VAUX(off2), the outputs are disabled. Once the outputs are disabled, the bias current of the IC is reduced, allowing VAUX to charge back up. This mode of operation allows a dramatic reduction in the size of CAUX as not all the power required for startup needs to be stored by CAUX. This mode of operation is known as Dynamic Self Supply (DSS). Figure 40 shows the relationship between VAUX(on), VAUX(off1), VAUX(off2) and UV. As shown in Figure 40, the outputs are not enabled until the UV fault is removed and VAUX reaches VAUX(on).
http://onsemi.com
16
NCP1282
VAUX(on) VAUX(off1) VAUX Vinhibit
VUVOV VREF VSS
Vout1
Figure 40. Startup Circuit Waveforms
The startup regulator is disabled by biasing VAUX above VAUX(on). This feature allows the NCP1282 to operate from an independent 12 V supply. If operating from an independent supply, the Vin and VAUX pins should be connected together. The independent supply should maintain VAUX above VAUX(on). Otherwise, the Output Latch will not be SET and the outputs will remain OFF after a fault condition is removed. The startup circuit sources current into the VAUX pin. It is recommended to place a diode between CAUX and the auxiliary supply as shown in Figure 41. This allows the NCP1282 to charge CAUX while preventing the startup regulator from sourcing current into the auxiliary supply.
Auxiliary Supply or Independent Supply VAUX IAUX Disable CAUX Isupply
and the 5.0 V reference load must be considered to correctly size CAUX. The current consumption due to external gate charge is calculated using Equation 1.
IAUX(gate charge) + f @ QG
(eq. 1)
Vin
Istart
Figure 41. Recommended VAUX Configuration
CAUX provides power to the controller while operating in the self-bias or DSS mode. During the converter powerup, CAUX must be sized such that a VAUX voltage greater than VAUX(off2) is maintained while the auxiliary supply voltage is building up. Otherwise, VAUX will collapse and the controller will turn OFF. Also, the VAUX discharge time (from 11.0 V to 9.5 V) must be greater that the soft-start charge period to assure the converter turns ON. The IC bias current, gate charge load on the outputs,
where, f is the operating frequency and QG is the gate charge. An internal supervisory circuit monitors VAUX and prevents excessive power dissipation if the VAUX pin is accidentally shorted. While VAUX is below 1.2 V, the startup circuit is disabled and a current source (Iinhibit) charges VAUX with a minimum current of 50 mA. Once VAUX reaches 1.2 V the startup circuit is enabled. Therefore it is imperative that VAUX is not loaded (driver, resistor divider, etc.) with more than 50 mA while VAUX is below 1.2 V. Otherwise, VAUX will not charge. If a load greater than 50 mA is present, a resistor can be placed between the Vin and VAUX pins to help charge VAUX to 1.2 V. The startup circuit is rated at a maximum voltage of 500 V. If the device operates in the DSS mode, power dissipation should be controlled to avoid exceeding the maximum power dissipation of the controller. If dissipation on the controller is excessive, a resistor can be placed in series with the Vin pin. This will reduce power dissipation on the controller and transfer it to the series resistor.
Line Under/Overvoltage Detector
The same pin is used for both line undervoltage (UV) and overvoltage (OV) detection using a novel architecture (patent pending). This architecture allows both the UV and OV levels to be set independently. Both the UV and OV detectors have a 100 mV hysteresis.
http://onsemi.com
17
NCP1282
The line voltage is sampled using a resistor divider as shown in Figure 42.
+ - OV Comparator VOVCOMP
Vin(UV) + VUV Vin(OV) + VOV
(R1 ) R2) R2 R1)
(eq. 1)
(R1 ) R2) ) (Ioffset(UVOV) R2
+ - Vin R1 + UVOV CUVOV -
(eq. 2)
3.0 V + - UV Comparator VUVCOMP
2.0 V + - 2.5 V
R2
+ -
The undervoltage threshold is trimmed during manufacturing to obtain "3% accuracy allowing a tighter power stage design. Once the line voltage is within the operating range, and VAUX reaches VAUX(on), the outputs are enabled and a soft-start sequence commences. If a UV or OV fault is detected afterwards, the converter enters a soft-stop mode. A small capacitor is required (>1000 pF) from the UVOV pin to GND to prevent oscillation of the UVOV pin and filter line transients.
Line Feedforward
Ioffset(UVOV)
Figure 42. Line UVOV Detectors
A UV condition exists if the UVOV voltage is below VUV, typically 2.0 V. The ratio of R1 and R2 determines the UV turn threshold. Once the UVOV voltage exceeds 2.5 V, an internal current source (Ioffset(UVOV)) sinks 50 mA into the UVOV pin. This will clamp the UVOV voltage at 2.5 V while the current across R1 is less than Ioffset(UVOV). If the input voltage continues to increase, the 50 mA source will be overridden and the voltage at the UVOV pin will increase. An OV condition exists if the UVOV voltage exceeds VOV, typically 3.0 V. Figure 43 shows the relationship between UVOV and Vin.
Vin (V)
The NCP1282 incorporates line feedforward (FF) to limit the maximum volt-second product. It is the line voltage times the ON time. This limit prevent saturation of the transformer in forward and flyback topologies. Another advantage of feedforward is a controller frequency gain independent of line voltage. A constant gain facilitates frequency compensation of the converter. Feedforward is implemented by generating a ramp proportional to Vin and comparing it to the error signal. The error signal solely controls the duty cycle while the input voltage is fixed. If the line voltage changes, the FF Ramp slope changes and duty cycle is immediately adjusted instead of waiting for the change to propagate around the feedback loop and be reflected back on the error signal. The FF Ramp is generated with an R-C (RFFCFF) divider from the input line as shown in Figure 44. The divider is selected such that the FF Ramp reaches 3.0 V in the desired maximum ON time. The FF Ramp terminates by effectively grounding CFF during the converter OFF time. This can be triggered by the FF Ramp reaching 3.0 V, or any other condition that limits the duty cycle.
Vin
VUVOV (V)
VUVCOMP VUVOV
To PWM and VS Comparators
RFF FF
IRFF 3V 0V
VOVCOMP
FF Reset
IFF(D)
CFF
ton T
Time
Figure 43. UVOV Detectors Typical Waveforms
Figure 44. Feed Forward Ramp Generation
While the internal current source is disabled, the UVOV voltage is solely determined by the ratio of R1 and R2. The input voltage at which the converter turns ON is given by Equation 1. Once the internal current source is enabled, the absolute value of R1 together with the ratio of R1 and R2 determine the turn OFF threshold as shown in Equation 2.
The FF pin is effectively grounded during power or during standby mode to prevent the FF pin from charging up to Vin.
http://onsemi.com
18
NCP1282
The minimum value of RFF is determined by the FF Ramp discharge current (IFF(D)). The current through RFF (IRFF) should be at least ten times smaller than IFF(D) for a sharp FF Ramp transition. Equations 3 and 4 are used to determine RFF and CFF.
Vin v RFF 10 IFF(D) CFF + ln
Vin Vin -3 V
1.0 A. If a higher drive capability is required, an external driver stage can be easily added as shown in Figure 46.
VAUX
(eq. 3) Output
D f RFF
(eq. 4)
where, f is the operating frequency. It is recommended to bias the FF circuit with enough current to provide good noise immunity.
PWM Comparator
OUT1 or OUT2
Figure 46. Discrete Boost Drive Stage
In steady state operation, the PWM Comparator adjusts the duty cycle by comparing the error signal to the FF Ramp. The error signal is fed into the VEA pin. The VEA pin can be driven directly with an optocoupler without the need of an external pullup resistor as shown in Figure 45. In some instances, it may be required to have a pullup resistor smaller than the internal resistor (R4) to adjust the gain of the isolation stage. This is easily accomplished by connecting an external resistor (REA) in parallel with R4. REA is connected between the VREF and VEA pins. The effective pullup resistance is the parallel combination of R4 and REA.
VREF PWM Comparator - + + - FF 3V FF Ramp 0V 20 kW 2 kW 270 kW VEA REA (Optional) Feedback Signal
0.2 V
Figure 45. Optocoupler Driving VEA Input
OUT1 drives the main MOSFET, and OUT2 drives a low side P-Channel active clamp MOSFET. A high side N-Channel active clamp MOSFET or a synchronous rectifier can also be driven by inverting OUT2. OUT2 is purposely sized smaller than OUT1 because the active clamp MOSFET only sees the magnetizing current. Therefore, a smaller active clamp MOSFET with less input capacitance can be used compared to the main switch. Once VAUX reaches VAUX(on) (typically 11.0 V), the internal startup circuit is disabled and the outputs are enabled if no faults are present. Otherwise, the outputs remain disabled until the fault is removed and VAUX reaches VAUX(on). The outputs are disabled after a soft-stop sequence if VAUX is below VAUX(on) or if VAUX reaches 8.5 V. The outputs are biased directly from VAUX and their high state voltage is approximately VAUX. Therefore, the auxiliary supply voltage should not exceed the maximum gate voltage of the main or active clamp MOSFET. The high current drive capability of the outputs will generate inductance-induced spikes if inductance is not reduced on the outputs. This can be done by reducing the connection length between the drivers and their loads and using wide connections.
Overlap Delay
The drive of the VEA pin is simplified by internally incorporating a series diode and resistor. The series diode provides a 0.7 V offset between the VEA input and the PWM Comparator inverting input. It allows reaching zero duty cycle without the need of pulling the VEA pin all the way to GND. The outputs are enabled if the VEA voltage is approximately 0.5 V above the valley of the FF Ramp.
Outputs
The overlap delay prevents simultaneous conduction of the main and active clamp MOSFETs. The secondary output, OUT2, precedes OUT1 during a low to high transition and trails OUT1 during a high to low transition. Figure 47 shows the relationship between OUT1 and OUT2.
tD (Leading) OUT1 OUT2 tD (Trailing)
The NCP1282 has two in-phase output drivers with an adjustable overlap delay (tD). The main output, OUT1, has a source resistance of 4.0 W (typ) and a sink resistance of 2.5 W (typ). The secondary output, OUT2, has a source and a sink resistance of 12 W (typ). OUT1 is rated at a maximum of 2.0 A and OUT2 is rated at a maximum of
http://onsemi.com
19
Figure 47. Output Timing Diagram
NCP1282
The output overlap delay is adjusted by connecting a resistor, RD, from the tD pin to ground. The overlap delay is proportional to RD. A minimum delay of 20 ns is obtained by grounding the tD pin. The leading delay is purposely made longer than the trailing delay. This allows the user to optimize the delay for the turn on transition of the main switch and ensure the active clamp switch always exhibits zero volt switching.
Analog and Power Ground (PGND)
voltage (VRTCT(valley)), typically 2.0 V, IRTCT turns OFF allowing CT to charge back up through RT. The resulting waveform on the RTCT pin has a sawtooth like shape.
VREF RT RTCT IRTCT 3V 2V Enable CT
The NCP1282 has an analog ground, GND, and a power ground, PGND, terminal. GND is used for analog connections such as VREF, RTCT, feedforward among others. PGND is used for high current connections such as the internal output drivers. It is recommended to have independent analog and power ground planes and connect them at a single point, preferably at the ground terminal of the system. This will prevent high current flowing on PGND from injecting noise in GND. The PGND connection should be as short and wide as possible to reduce inductance-induced spikes.
Oscillator
Figure 48. Oscillator Configuration
The oscillator frequency and maximum duty cycle are set by an RTCT divider from VREF as shown in Figure 48. A 500 mA current source (IRTCT) discharges the timing capacitor (CT) upon reaching its peak threshold (VRTCT(peak)), typically 3.0 V. Once CT reaches its valley
tRTCT(D) + RTCT ln (IRTCT (IRTCT
OUT2 is set high once VRTCT(valley) is reached, followed by OUT1 delayed by the overlap delay. Once VRTCT(peak) is reached, OUT1 goes low, followed by OUT2 delayed by tD. The duty cycle is the CT charge time (tRTCT(C)) minus the overlap delay over the total charge and discharge (tRTCT(D)) times. The charge and discharge times are calculated using Equations 5 and 6. However, these equations are an approximation as they do not take into account the propagation delays of the internal comparator.
tRTCT(C) + RTCT ln VRTCT(valley)-VREF VRTCT(peak)-VREF
(eq. 5)
RT) ) VRTCT(peak)-VREF RT) ) VRTCT(valley)-VREF
(eq. 6)
The duty cycle, DC, is given by Equation 7.
D+ tRTCT(C)-tD tRTCT(C) ) tRTCT(D) D+
(eq. 7)
Substituting Equations 5, 6, and 7, and after a little algebraic manipulation and replacing values, it simplifies to:
-R D C
t TT
ln ln
VRTCT(valley)-VREF VRTCT(peak)-VREF
VRTCT(valley)-VREF VRTCT(peak)-VREF
(IRTCT RT))VRTCT(peak)-VREF (IRTCT)VRTCT(valley)-VREF
(eq. 8)
It can be observed that D is set by RT, CT and tD. This equation has two variables and can be solved iteratively. In general, the time delay is a small portion of the ON time and can be ignored as a first approximation. RT is then selected
f+ 1 RTCT ln
VRTCT(valley)-VREF VRTCT(peak)-VREF
to achieve a given duty cycle. Once the RT is selected, CT is chosen to obtain the desired operating frequency using Equation 9.
(IRTCT RT))VRTCT(peak)-VREF (IRTCT RT))VRTCT(valley)-VREF
(eq. 9)
Figures 23 through 26 show the frequency and duty cycle variation vs RT for several CT values. RT should not be less than 6.0 kW. Otherwise, the RTCT charge current will exceed the pulldown current and the oscillator will be in an undefined state.
Synchronization
A proprietary bidirectional frequency synchronization architecture allows multiple NCP1282 to synchronize in a master-slave configuration. It can synchronize to frequencies above or below the free running frequency.
http://onsemi.com
20
NCP1282
The SYNC pin is in a high impedance mode during the charging of the RTCT Ramp. In this period the oscillator accepts an external SYNC pulse. If no pulse is detected upon reaching the peak of the RTCT Ramp, a 100 ns SYNC pulse is generated. The SYNC pulse is generated by internally pulling the SYNC pin to VREF. The peak voltage of the SYNC pin is typically 4.3 V. Once the 100 ns timer expires, the pin goes back into a high impedance mode and an external resistor is required for pulldown as shown in Figure 49.
VREF RT RTCT CT SYNC RSYNC MASTER CONTROLLER SYNC RSYNC1 SYNC RSYNC2 SLAVE CONTROLLER
Figure 50. Master-Slave Configuration 5.0 V Reference
Figure 49. SYNC Pulse
The slew rate of the sync pin is determined by the pin capacitance and external pulldown resistor. The maximum source current of the SYNC pin is 1.0 mA. The resistor is sized to allow the SYNC pin to discharge before the start of the next cycle. If an external pulse is received on the SYNC pin before the internal pulse is generated, the controller enters the slave mode of operation. Once operation in slave mode commences, CT begins discharging and the RTCT Ramp upper threshold is increased to 4.0 V. If a controller in slave mode does not receive a sync pulse before reaching the RTCT Ramp peak voltage (4.0 V), the upper threshold is reset back to 3.0 V and the converter reverts to operation in master mode. To guarantee the converter stays in slave mode, the minimum clock period of the master controller has to be less than the RTCT charge time from 2.0 V to 4.0 V. Two NCP1282's are synchronized by connecting their SYNC pins together. The first device that generates a sync pulse during powerup becomes the master. A diode connected as shown in Figure 50 can be used to permanently set one controller as the master. The diode prevents the master from receiving the SYNC pulse of the slave controller.
The NCP1282 has a precision 5.0 V reference output. It is a buffered version of the internal reference. The 5.0 V reference is biased directly from VAUX and it can supply up to 5.0 mA. Load regulation is 50 mV and line regulation is 100 mV within the specified operating range. It is required to bypass the reference with a capacitor. The capacitor is used for compensation of the internal regulator and high frequency noise filtering. The capacitor should be placed across the VREF and GND pins. In most applications a 0.1 mF will suffice. A bigger capacitor may be required to reduce the voltage ripple caused by the oscillator current. The recommended capacitor range is between 0.047 mF and 1.0 mF. During powerup, the 5.0 V reference is enabled once VAUX reaches VAUX(on) and a UV fault is not present. Otherwise, the reference is enabled once the UV fault is removed and VAUX reaches VAUX(on). Once a UV fault is detected after the reference has been enabled, the reference is disabled after the soft-stop sequence is complete if the UV fault is still present. If the UV fault is removed before soft-stop is complete, the reference is not disabled.
Application Information
ON Semiconductor provides an electronic design tool, a demonstration board and an application note to facilitate design of the NCP1282 and reduce development cycle time. All the tools can be downloaded or ordered at www.onsemi.com. The electronic design tool allows the user to easily determine most of the system parameters of an active clamp forward converter. The tool evaluates the power and active clamp stages as well as the frequency response of the system. The tool allows the user to design a dual output converter. The demo board delivers 240 W and has a 12 V and a 5 V output. The circuit schematic is shown in Figure 51. The converter design is described in Application Note ANDxxxx.
http://onsemi.com
21
NCP1282
Figure 51. Circuit Schematic http://onsemi.com
22
NCP1282
PACKAGE DIMENSIONS
SO-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
The products described herein (NCP1282), may be covered by one or more of the following U.S. patents: 6,771,138. There may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
http://onsemi.com
23
NCP1282/D

▲Up To Search▲

Price & Availability of NCP1282

	To Download NCP1282 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .